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DATA SHEET
MOS INTEGRATED CIRCUIT
PD4481161, 4481181, 4481321, 4481361
8M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION
Description
The PD4481161 is a 524,288-word by 16-bit, the PD4481181 is a 524,288-word by 18-bit, the PD4481321 is a 262,144-word by 32-bit and the PD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The PD4481161, PD4481181, PD4481321 and PD4481361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The PD4481161, PD4481181, PD4481321 and PD4481361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The PD4481161, PD4481181, PD4481321 and PD4481361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
Features
* Low voltage core supply : VDD = 3.3 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y) VDD = 2.5 0.125 V (-C75, -C85, -C75Y, -C85Y) * Synchronous operation * Operating temperature : TA = 0 to 70 C (-A65, -A75, -A85, -C75, -C85) TA = -40 to +85 C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y) * 100 percent bus utilization * Internally self-timed write control * Burst read / write : Interleaved burst and linear burst sequence * Fully registered inputs and outputs for flow through operation * All registers triggered off positive clock edge * 3.3V or 2.5V LVTTL Compatible : All inputs and outputs * Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz) * Asynchronous output enable : /G * Burst sequence selectable : MODE * Sleep mode : ZZ (ZZ = Open or Low : Normal operation) * Separate byte write enable : /BW1 to /BW4 (PD4481321 and PD4481361) /BW1 and /BW2 (PD4481161 and PD4481181) * Three chip enables for easy depth expansion * Common I/O using three state outputs
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Document No. M15561EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan
The mark
shows major revised points.
2001
PD4481161, 4481181, 4481321, 4481361
Ordering Information
Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 0.165 3.3 V LVTTL
Note
(1/2)
I/O Interface Operating Temperature C 0 to 70 100-pin PLASTIC LQFP (14 x 20) Package
PD4481161GF-A65 PD4481161GF-A75 PD4481161GF-A85 PD4481181GF-A65 PD4481181GF-A75 PD4481181GF-A85 PD4481321GF-A65 PD4481321GF-A75 PD4481321GF-A85 PD4481361GF-A65 PD4481361GF-A75 PD4481361GF-A85 PD4481161GF-C75 PD4481161GF-C85 PD4481181GF-C75 PD4481181GF-C85 PD4481321GF-C75 PD4481321GF-C85 PD4481361GF-C75 PD4481361GF-C85
6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5
3.3 V or 2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).
2
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
(2/2)
Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 0.165 3.3 V LVTTL
Note
I/O Interface
Operating Temperature C -40 to +85
Package
PD4481161GF-A65Y PD4481161GF-A75Y PD4481161GF-A85Y PD4481181GF-A65Y PD4481181GF-A75Y PD4481181GF-A85Y PD4481321GF-A65Y PD4481321GF-A75Y PD4481321GF-A85Y PD4481361GF-A65Y PD4481361GF-A75Y PD4481361GF-A85Y PD4481161GF-C75Y PD4481161GF-C85Y PD4481181GF-C75Y PD4481181GF-C85Y PD4481321GF-C75Y PD4481321GF-C85Y PD4481361GF-C75Y PD4481361GF-C85Y
6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5
100-pin PLASTIC LQFP (14 x 20)
3.3 V or 2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).
Data Sheet M15561EJ3V0DS
3
PD4481161, 4481181, 4481321, 4481361
Pin Configurations
/xxx indicates active low signal.
100-pin PLASTIC LQFP (14 x 20) [PD4481161GF, PD4481181GF]
Marking Side
/BW2 /BW1 /CKE /CE2 ADV CE2 CLK /WE A17 VDD VSS /CE NC NC NC A6 A7 A8 A9 /G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 VSS VDD VDD VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2, NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A18 NC NC VDDQ VSSQ NC I/OP1, NC I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS VSS VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
A10
A11
A12
A13
A14
A15
Remark
Refer to Package Drawing for the 1-pin index mark.
4
Data Sheet M15561EJ3V0DS
A16
NC
VDD
NC
PD4481161, 4481181, 4481321, 4481361
Pin Identifications
[PD4481161GF, PD4481181GF]
Symbol A0 to A18 Pin No. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83, 80 I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 I/OP1, NC Note I/OP2, NC ADV /CE, CE2, /CE2 /WE /BW1, /BW2 /G CLK /CKE MODE
Note
Description Synchronous Address Input
Synchronous Data In, Synchronous / Asynchronous Data Out Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation
74 24 85 98, 97, 92 88 93, 94 86 89 87 31
ZZ VDD VSS VDDQ VSSQ NC
64 15, 16, 41, 65, 91 14, 17, 40, 66, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96
Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection
Note NC (No Connection) is used in the PD4481161GF. I/OP1 and I/OP2 are used in the PD4481181GF.
Data Sheet M15561EJ3V0DS
5
PD4481161, 4481181, 4481321, 4481361
100-pin PLASTIC LQFP (14 x 20)
[PD4481321GF, PD4481361GF]
Marking Side
/BW4 /BW3 /BW2 /BW1 /CKE /CE2 ADV CE2 CLK /WE A17 VDD VSS /CE NC A6 A7 A8 A9 /G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3, NC I/O17 I/O18 VDDQ VSSQ I/O19 I/O20 I/O21 I/O22 VSSQ VDDQ I/O23 I/O24 VSS VDD VDD VSS I/O25 I/O26 VDDQ VSSQ I/O27 I/O28 I/O29 I/O30 VSSQ VDDQ I/O31 I/O32 I/OP4, NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/OP2, NC I/O16 I/O15 VDDQ VSSQ I/O14 I/O13 I/O12 I/O11 VSSQ VDDQ I/O10 I/O9 VSS VSS VDD ZZ I/O8 I/O7 VDDQ VSSQ I/O6 I/O5 I/O4 I/O3 VSSQ VDDQ I/O2 I/O1 I/OP1, NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
A10
A11
A12
A13
A14
A15
Remark Refer to Package Drawing for the1-pin index mark.
6
Data Sheet M15561EJ3V0DS
A16
NC
VDD
NC
PD4481161, 4481181, 4481321, 4481361
[PD4481321GF, PD4481361GF]
Symbol A0 to A17 Pin No. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83 I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 I/OP1, NC Note I/OP2, NC I/OP3, NC I/OP4, NC ADV /CE, CE2, /CE2 /WE /BW1 to /BW4 /G CLK /CKE MODE
Note Note Note
Description Synchronous Address Input
Synchronous Data In, Synchronous / Asynchronous Data Out
51 80 1 30 85 98, 97, 92 88 93, 94, 95, 96 86 89 87 31
Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation
ZZ VDD VSS VDDQ VSSQ NC
64 15, 16, 41, 65, 91 14, 17, 40, 66, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 38, 39, 42, 43, 84
Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection
Note NC (No Connection) is used in the PD4481321GF. I/OP1 to I/OP4 are used in the PD4481361GF.
Data Sheet M15561EJ3V0DS
7
PD4481161, 4481181, 4481321, 4481361
Block Diagrams
[PD4481161, PD4481181]
A0 to A18 Address register 0
19 A1 A0 ADV K 17 A1' A0' 19
MODE CLK /CKE
K
Burst logic
19
Write address register
19
Sense amplifiers
ADV /BW1 /BW2 /WE
Memory Cell Array
Output buffers
Data steering
Write registry and data coherency control logic
Write drivers
1,024 rows 512 x 16 columns (8,388,608 bits) 512 x 18 columns (9,437,184 bits)
16/18
16/18
I/O1 to I/O16 I/OP1, I/OP2
E 16/18
16/18
Input register E
/G /CE CE2 /CE2 ZZ
Read logic
Power down control
Burst Sequence
PD4481181] [PD4481161,
Interleaved Burst Sequence Table (MODE = VDD)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A18 to A2, A1, A0 A18 to A2, A1, /A0 A18 to A2, /A1, A0 A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0
8
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
[PD4481321, PD4481361]
A0 to A17 Address register 0
18 A1 A0 ADV K 16 A1' A0' 18
MODE CLK /CKE
K
Burst logic
18
Write address register
18
Memory Cell Array
Sense amplifiers
Output buffers
Data steering
ADV /BW1 /BW2 /BW3 /BW4 /WE
Write registry and data coherency control logic
Write drivers
1,024 rows 256 x 32 columns (8,388,608 bits) 256 x 36 columns (9,437,184 bits)
32/36
32/36
I/O1 to I/O32 I/OP1 to I/OP4
E 32/36
32/36
Input register E
/G /CE CE2 /CE2 ZZ
Read logic
Power down control
PD4481361] [PD4481321,
Interleaved Burst Sequence Table (MODE = VDD)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A17 to A2, A1, A0 A17 to A2, A1, /A0 A17 to A2, /A1, A0 A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0
Data Sheet M15561EJ3V0DS
9
PD4481161, 4481181, 4481321, 4481361
State Diagram
DS DS
BURST DS
DESELECT
READ DS DS
WRITE
WRITE READ BEGIN READ READ BEGIN WRITE WRITE
READ
BURST
BURST
WRITE
WRITE BURST BURST READ
READ BURST WRITE BURST
Command DS Read Write Burst
Operation Deselect New Read New Write Burst Read, Burst Write or Continue Deselect
Remarks 1. States change on the rising edge of the clock. 2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only blocks the clock (CLK) input and does not change the state of the device.
10
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Asynchronous Truth Table
Operation Read Cycle Read Cycle Write Cycle Deselected /G L H x x I/O Dout High-Z High-Z, Din High-Z
Remark
x : don't care
Synchronous Truth Table
Operation Deselected Deselected Deselected Continue Deselected Read Cycle / Begin Burst Read Cycle / Continue Burst Write Cycle / Begin Burst Write Cycle / Continue Burst Write Cycle / Write Abort Write Cycle / Write Abort Stall / Ignore Clock Edge /CE H x x x L x L x L x x CE2 x L x x H x H x H x x /CE2 x x H x L x L x L x x ADV L L L H L H L H L H x /WE x x x x H x L x L x x /BWs x x x x x x L L H H x /CKE L L L L L L L L L L H CLK LH LH LH LH LH LH LH LH LH LH LH I/O High-Z High-Z High-Z High-Z Dout Dout Din Din High-Z High-Z - Address None None None None External Next External Next External Next Current 2 Note 1 1 1 1
Notes
1. Deselect status is held until new "Begin Burst" entry. 2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will be performed during the Ignore Clock Edge cycle.
Remarks 1. x : don't care 2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. /BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
Data Sheet M15561EJ3V0DS
11
PD4481161, 4481181, 4481321, 4481361
Partial Truth Table for Write Enables
[PD4481161, PD4481181]
Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / All Bytes Write Abort / NOP /WE H L L L L /BW1 x L H L H /BW2 x H L L H
Remark
x : don't care
PD4481361] [PD4481321,
Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / Byte 3 (I/O [17:24], I/OP3) Write Cycle / Byte 4 (I/O [25:32], I/OP4) Write Cycle / All Bytes Write Abort / NOP /WE H L L L L L L /BW1 x L H H H L H /BW2 x H L H H L H /BW3 x H H L H L H /BW4 x H H H L L H
Remark
x : don't care
ZZ (Sleep) Truth Table
ZZ Chip Status Active Active Sleep
0.2 V
Open
VDD - 0.2 V
12
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD Conditions -A65, -A75, -A85 -A65Y, -A75Y, -A85Y -C75, -C85 -C75Y, -C85Y Output supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Tstg VDDQ VIN VI/O TA -A65, -A75, -A85, -C75, -C85 -A65Y, -A75Y, -A85Y, -C75Y, -C85Y -0.5 -0.5 -0.5 0 -40 -55
Note Note
MIN. -0.5
TYP.
MAX. +4.0
Unit V
-0.5
+3.0
VDD VDD + 0.5 VDDQ + 0.5 70 +85 +125
V V V C
C
Note -2.0 V (MIN.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions
Parameter Symbol Conditions -A65, -A75, -A85 -A65Y, -A75Y, -A85Y MIN. Supply voltage 2.5 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage 3.3 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage VDDQ VIH VIL 3.135 2.0 -0.3
Note
(1/2)
Unit
TYP. 3.3
MAX. 3.465 V
VDD
3.135
VDDQ VIH VIL
2.375 1.7 -0.3
Note
2.5
2.9 VDDQ + 0.3 +0.7
V V V
3.3
3.465 VDDQ + 0.3 +0.8
V V V
Note -0.8 V (MIN.) (Pulse width : 2 ns) Recommended DC Operating Conditions
Parameter Symbol Conditions -C75, -C85 -C75Y, -C85Y MIN. Supply voltage Output supply voltage High level input voltage Low level input voltage VDD VDDQ VIH VIL 2.375 2.375 1.7 -0.3
Note
(2/2)
Unit
TYP. 2.5 2.5
MAX. 2.625 2.625 VDDQ + 0.3 +0.7 V V V V
Note -0.8 V (MIN.) (Pulse width : 2 ns)
Data Sheet M15561EJ3V0DS
13
PD4481161, 4481181, 4481321, 4481361
DC Characteristics (VDD = 3.3 0.165 V or 2.5 0.125 V)
Parameter Input leakage current I/O leakage current Operating supply current Symbol ILI ILO IDD Test condition VIN (except ZZ, MODE) = 0 V to VDD VI/O = 0 V to VDDQ, Outputs are disabled. Device selected, Cycle = MAX., VIN VIL or VIN VIH, II/O = 0 mA -A65 -A65Y -A75, -C75 -A75Y, -C75Y -A85, -C85 -A85Y, -C85Y Standby supply current ISB Device deselected, Cycle = 0 MHz, VIN VIL or VIN VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz, VIN 0.2 V or VIN VDD - 0.2 V, VI/O 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX., VIN VIL or VIN VIH Power down supply current 2.5 V LVTTL Interface High level output voltage VOH IOH = -2.0 mA IOH = -1.0 mA Low level output voltage VOL IOL = +2.0 mA IOL = +1.0 mA 3.3 V LVTTL Interface High level output voltage Low level output voltage VOH VOL IOH = -4.0 mA IOL = +8.0 mA 2.4 0.4 V V 1.7 2.1 0.7 0.4 V V ISBZZ ZZ VDD - 0.2 V, VI/O VDDQ + 0.2 V 15 mA 110 15 30 mA 200 225 MIN. -2 -2 TYP. MAX. +2 +2 250 Unit
A A
mA
Capacitance (TA = 25 C, f = 1MHz)
Parameter Input capacitance Input / Output capacitance Clock input capacitance Symbol CIN CI/O Cclk VIN = 0 V VI/O = 0 V Vclk = 0 V Test condition MIN. TYP. MAX. 6.0 8.0 6.0 Unit pF pF pF
Remark
These parameters are periodically sampled and not 100% tested.
14
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
AC Characteristics (VDD = 3.3 0.165 V or 2.5 0.125 V) AC Test Conditions 2.5 V LVTTL Interface Input waveform (Rise / Fall time 2.4 ns)
2.4 V 1.2 V VSS Test points 1.2 V
Output waveform
1.2 V
Test points
1.2 V
3.3 V LVTTL Interface Input waveform (Rise / Fall time 3.0 ns)
3.0 V 1.5 V VSS Test points 1.5 V
Output waveform
1.5 V
Test points
1.5 V
Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) Figure External load at test
ZO = 50 I/O (Output) 50 CL
VT = +1.2 V / +1.5 V
Remark CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M15561EJ3V0DS
15
PD4481161, 4481181, 4481321, 4481361
Read and Write Cycle (2.5 V LVTTL Interface)
Parameter Symbol -A65, -A75, -C75 -A65Y, -A75Y, -C75Y (117 MHz) Standard Cycle time Clock access time Output enable access time Clock high to output active Clock high to output change Output enable to output active Output disable to output High-Z Clock high to output High-Z Clock high pulse width Clock low pulse width Setup times Address TKHKH TKHQV TGLQV TKHQX1 TKHQX2 TGLQX TGHQZ TKHQZ TKHKL TKLKH TAVKH Alias TCYC TCD TOE TDC1 TDC2 TOLZ TOHZ TCZ TCH TCL TAS TADVS TCES TCSS TDS TWS TAH TADVH TCEH TCSH TDH TWH TZZE TZZR - - 8.6 8.6 - - 10 10 ns ns 0.5 - 0.5 - ns MIN. 8.6 - - 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. - 7.5 3.5 - - - 3.5 5 - - - -A85, -C85 -A85Y, -C85Y (100 MHz) MIN. 10 - - 2.5 2.5 0 0 2.5 2.5 2.5 2 MAX. - 8.5 3.5 - - - 3.5 5 - - - ns ns ns ns ns ns ns ns ns ns ns 1 1 1, 2 1, 2 Unit Note
Address advance TADVVKH Clock enable Chip enable Data in Write enable Hold times Address TEVKH TCVKH TDVKH TWVKH TKHAX
Address advance TKHADVX Clock enable Chip enable Data in Write enable Power down entry time Power down recovery time TKHEX TKHCX TKHDX TKHWX TZZE TZZR
Notes 1. Transition is measured 200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).
16
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Read and Write Cycle (3.3 V LVTTL Interface)
Parameter Symbol -A65 -A65Y (133 MHz) Standard Cycle time Clock access time Output enable access time Clock high to output active Clock high to output change Output enable to output active Output disable to output High-Z Clock high to output High-Z Clock high pulse width Clock low pulse width Setup times Address TKHKH TKHQV TGLQV TKHQX1 TKHQX2 TGLQX TGHQZ TKHQZ TKHKL TKLKH TAVKH Alias TCYC TCD TOE TDC1 TDC2 TOLZ TOHZ TCZ TCH TCL TAS TADVS TCES TCSS TDS TWS TAH TADVH TCEH TCSH TDH TWH TZZE TZZR - - 7.5 7.5 - - 8.6 8.6 - - 10 10 ns ns 0.5 - 0.5 - 0.5 - ns MIN. 7.5 - - 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. - 6.5 3.5 - - - 3.5 5 - - - -A75 -A75Y (117 MHz) MIN. 8.6 - - 2.5 2.5 0 0 2.5 2.5 2.5 1.5 MAX. - 7.5 3.5 - - - 3.5 5 - - - -A85 -A85Y (100 MHz) MIN. 10 - - 2.5 2.5 0 0 2.5 2.5 2.5 2 MAX. - 8.5 3.5 - - - 3.5 5 - - - ns ns ns ns ns ns ns ns ns ns ns 1 1 1, 2 1, 2 Unit Note
Address advance TADVVKH Clock enable Chip enable Data in Write enable Hold times Address TEVKH TCVKH TDVKH TWVKH TKHAX
Address advance TKHADVX Clock enable Chip enable Data in Write enable Power down entry time Power down recovery time TKHEX TKHCX TKHDX TKHWX TZZE TZZR
Notes 1. Transition is measured 200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).
Data Sheet M15561EJ3V0DS
17
PD4481161, 4481181, 4481321, 4481361
READ / WRITE CYCLE
1 2 TKHKH 3 4 5 6 7 8 9 10
CLK
TEVKH TKHEX TKHKL TKLKH
/CKE
TCVKH TKHCX
/CEs Note 1
TADVVKH TKHADVX
ADV
TWVKH TKHWX
/WE
TWVKH TKHWX
/BWs Note 2
Address
TAVKH
A1 TKHAX
A2
A3
A4
A5
A6
A7
Data In
High-Z
D (A1) TDVKH TKHDX
D (A2)
D (A2+1) TKHQX1
High-Z
D (A5) TGLQV TKHQZ High-Z TKHQX2 TGLQX
High-Z
TKHQX2 Q (A3)
Data Out
High-Z
Q (A4)
Q (A4+1)
Q (A6)
Q (A7)
TKHQV
TGHQZ
/G
Command
WRITE D (A1)
WRITE D (A2)
BURST WRITE D (A2+1)
READ Q (A3)
READ Q (A4)
BURST READ Q (A4+1)
WRITE D (A5)
READ Q (A6)
WRITE Q (A7)
DESELECT
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
18
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
NOP, STALL AND DESELECT CYCLE
1 2 3 4 5 6 7 8 9 10
CLK
/CKE
/CEs
ADV
/WE
/BWs
Address
A1
A2
A3
A4
A5
Data In
High-Z
D (A1)
High-Z
D (A4) TKHQZ
High-Z
Data Out
High-Z
Q (A2)
Q (A3)
High-Z
Q (A5) TKHQX2
High-Z
Command
WRITE D (A1)
READ Q (A2)
STALL
READ Q (A3)
WRITE D (A4)
STALL
NOP
READ Q (A5)
DESELECT
CONTINUE DESELECT
Data Sheet M15561EJ3V0DS
19
PD4481161, 4481181, 4481321, 4481361
POWER DOWN (ZZ) CYCLE
1 2 3 4 5 6 7 8 9 10 11 12
TKHKH
CLK
TKHKL TKLKH
/CKE
/CEs Note
ADV
/WE Note
/BWs
Address
A1
A2
/G
Data Out
High-Z
Q (A1)
High-Z
Q1 (A2)
Q2 (A2)
ZZ
TZZE TZZR
Power Down (ISBZZ) State
Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.3 in this figure) prior to power down state entry.
20
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A B
80 81
51 50
detail of lead end S C D R Q
100 1
31 30
F G H I
M
J
K P S
N
S
L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.00.2 20.00.2 14.00.2 16.00.2 0.825 0.575 0.32 +0.08 -0.07 0.13 0.65 (T.P.) 1.00.2 0.50.2 0.17 +0.06 -0.05 0.10 1.4 0.1250.075 3 +7 -3 1.7 MAX. S100GF-65-8ET-1
Data Sheet M15561EJ3V0DS
21
PD4481161, 4481181, 4481321, 4481361
Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the PD4481161, 4481181, 4481321 and 4481361. Types of Surface Mount Devices
PD4481161GF : 100-pin PLASTIC LQFP (14 x 20) PD4481181GF : 100-pin PLASTIC LQFP (14 x 20) PD4481321GF : 100-pin PLASTIC LQFP (14 x 20) PD4481361GF : 100-pin PLASTIC LQFP (14 x 20)
22
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Revision History
Edition/ Date This edition 3rd edition/ Dec. 2002 Throughout Page Previous edition Throughout Modification Addition Type of revision Location Description (Previous edition This edition)
- -
Preliminary Data Sheet Data Sheet Extended operating temperature products (TA = -40 to +85 C)
Data Sheet M15561EJ3V0DS
23
PD4481161, 4481181, 4481321, 4481361
[MEMO]
24
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
[MEMO]
Data Sheet M15561EJ3V0DS
25
PD4481161, 4481181, 4481321, 4481361
[MEMO]
26
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M15561EJ3V0DS
27
PD4481161, 4481181, 4481321, 4481361
ZEROSB is a trademark of NEC Electronics Corporation.
* The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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